As the dimensions of geometries in integrated circuits have scaled the transistor gate length has scaled smaller bringing the transistor source and drain closer together increasing short channel effects. As the source and drain diffusions get closer together, off current leakage increases due to drain induced barrier lowering allowing carriers to flow from drain to source. To reduce short channel effects halo implants with the same doping type as the substrate are added with an angled implant using the source and drain extension photo pattern. The angled implant adds doping under the edges of the gate adjacent to the source and drain extensions. This additional doping raises the threshold voltage of the transistor and increases the barrier height. When the transistor gate length gets very short the source and drain halo implants may overlap raising the channel doping and the barrier height, leading to lower transistor off current leakage.
To combat short channel effects in typical deep submicron transistors, the halo doping is increased to the extent that the carrier mobility and transistor drive (on-state) current are degraded due to increased carrier scattering from the high concentration of halo dopant atoms in the transistor channel.
Drain Extended MOS transistors (DEMOS) and Lateral Drain MOS transistors (LDMOS) are frequently used in parts of an integrated circuit to switch higher voltages. (high voltage input/output buffers and analog sub-circuits for example). The key feature that enables higher voltage operation in the DEMOS and LDMOS transistors is the presence of a lightly doped extended drain that either partially or fully depletes when a high voltage is applied to the drain. The voltage drop across the lightly doped extended drain lowers the surface electric field and voltage across the gate dielectric in the off state. This in turn allows the DEMOS and LDMOS transistor to switch at higher voltages and use a thin lower voltage gate dielectric for acceptable on-state performance.
The lightly doped drain extension may be formed by adding photo patterning and implantation steps to the process flow. To reduce cost the lightly doped drain extension may also be created using photo resist patterns and implantation steps already present in the process flow. (e.g. well and threshold voltage adjust implants). The DEMOS and LDMOS transistors may also share the same gate dielectric and source-side extension and halo implants as the core MOS transistors. This enables the DEMOS and LDMOS transistors with acceptable performance to be added to an integrated circuit processing flow without adding manufacturing cost.